Decreasing device size and increasing device density has traditionally been a high priority for the manufacturing of integrated circuits. Optical and electron beam (e-beam) lithography have been a driving force for device scaling. Conventional lithography is limited to about 80 nm pitch for single exposure patterning. While double and other multi-patterning processes can realize smaller pitch, these approaches are expensive and more complex.
Directed self-assembly (DSA), a technique that aligns self-assembling polymeric materials on a lithographically defined directing or guide pattern, is a potential option for extending current lithography beyond its pitch and resolution limits. The self-assembling materials, for example, are block copolymers (BCPs) that in the case of diblock copolymers consist of a “A” homopolymer covalently attached to a “B” homopolymer, which are deposited over a lithographically defined directing pattern on a semiconductor substrate. The lithographically defined directing pattern is a pre-pattern (hereinafter “DSA directing pattern”) that is encoded with spatial chemical and/or topographical information (e.g., chemical epitaxy and/or graphoepitaxy) and serves to direct the self-assembly process and the pattern formed by the self-assembling materials. Subsequently, by annealing the DSA polymers, the A polymer chains and the B polymer chains undergo phase separation to form an A polymer region and a B polymer region that are registered to the underlying DSA directing pattern to define a nanopattern (hereinafter “DSA pattern”), typically at a scale smaller than the scale of a DSA directing pattern. Then, by removing either the A polymer block or the B polymer block by wet chemical or plasma-etch techniques, a mask is formed for transferring the DSA pattern to the underlying semiconductor substrate.
Generating an e-beam pattern for lithographically defining the DSA directing pattern to accurately form the shape of the DSA pattern requires proper accounting of a multitude of physical effects that occur during the DSA process to form the DSA pattern. A typical DSA process employing e-beam lithography involves generating an e-beam pattern, writing the e-beam pattern on a resist layer overlying a semiconductor substrate, developing the resist layer to create the DSA directing pattern, spin coating the pre-patterned developed resist with BCP, and annealing and developing the BCP to form the DSA pattern, and etching the developed DSA pattern. Unfortunately, current approaches for generating an e-beam pattern for defining a DSA directing pattern to form a DSA pattern do not fully account for the physical effects that occur during the DSA process.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including generating an e-beam pattern for lithographically defining a DSA directing pattern to accurately form a DSA pattern. Moreover, it is desirable to provide methods for fabricating integrated circuits including generating an e-beam pattern for lithographically defining a DSA directing pattern that more fully account for the physical effects that occur during a DSA process. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.